Computational Lithography: AI designs chip circuits

Together with the EDA service provider Synopsys, the Dutch fab supplier ASML and the Taiwanese chip manufacturer TSMC, Nvidia wants to use AI algorithms and thus the strengths of its own accelerator chips, especially the hopper generation, in order to drastically reduce the calculation times of exposure masks. Nvidia calls the technology cuLitho.

Synopsys founder and boss Aart de Geus is quoted as saying that computing times have been reduced from weeks to days. ASML boss Peter Wennink also sees great advantages in computational lithography, especially in the era of extreme ultraviolet exposure (EUV) with a large numerical aperture (High Numerical Aperture, High-NA). The application of computational lithography should offer advantages, especially when scaling future chips. TSMC aims to begin the qualification process of cuLitho in their manufacturing facilities from June 2023, Nvidia CEO Jen-Hsun Huang said at the spring GTC opening speech.

If Nvidia itself has its way, they even want to be able to finish the two-week calculations “overnight” or in an 8-hour shift. 500 Hopper H100 systems are said to do the work of 40,000 CPU systems, although it is not entirely clear how many Hopper H100 accelerators or CPUs are working in the systems. Elsewhere, Nvidia speaks of a factor of 40, which an H100 achieves compared to the CPU calculation.

The production of microchips is becoming increasingly complex. Not only the sheer number, but also the size of the individual circuits is increasingly pushing the limits of what is imaginable and physically feasible.

One of the problems is the so-called mask. Like an exposure stencil, the circuits that are to be exposed on the silicon wafer are drawn on it.

For decades, however, the wavelength of the light used, typically 193 nanometers and 13.5 nanometers in EUV production, has not been sufficient to keep up with the structure sizes. In order to correctly expose the tiny structures, not only a complex system of mirrors is used to reduce the size of the mask structures, but also a liquid that has a lower refractive index than air. Hence the name immersion lithography.

The physical mask must now be adjusted in such a way that the correct circuit diagram, including the various distortions, is ultimately projected onto the silicon wafer. For masks for microchips with tens of billions of transistors and using high-NA EUV exposure, the calculations required are so extensive that conventional servers need several days, if not weeks.

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